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4.5.11. DDR Bandwidth Test

4.5.11.1. Test Principle

DDR (Double Data Rate) memory bandwidth is a key performance metric for measuring the data transfer capability of a memory system. It reflects the amount of data that can be transferred per unit time, typically measured in MB/s or GB/s. By executing specific memory operations and measuring their execution time, the memory bandwidth performance can be estimated. The main test operations are: Copy, Scale, Add, and Triad.

1. Copy Operation:

for (j=0; j<STREAM_ARRAY_SIZE; j++)
    c[j] = a[j];

  • This operation copies data from array a[] to array c[]. It involves only memory read and write, thus measuring pure memory bandwidth.

2. Scale Operation:

for (j=0; j<STREAM_ARRAY_SIZE; j++)
    b[j] = scalar * c[j];

  • This operation multiplies each element of array c[] by a constant scalar and stores the result into array b[]. Bandwidth is measured through reading c[] and writing to b[].

3. Add Operation:

for (j=0; j<STREAM_ARRAY_SIZE; j++)
    c[j] = a[j] + b[j];

  • This operation adds corresponding elements from arrays a[] and b[], storing the result in array c[]. It reads two arrays and writes to a third, representing a typical two-read, one-write memory access pattern.

4. Triad Operation:

for (j=0; j<STREAM_ARRAY_SIZE; j++)
    a[j] = b[j] + scalar * c[j];

  • This is a more complex operation that performs a fused multiply-add (FMA) using elements from arrays b[] and c[] with a scalar multiplier, then stores the result in array a[]. It combines memory access with computation.

4.5.11.2. Preparation

1. Confirm DDR Type and Frequency: Different DDR types (e.g., LPDDR4) and frequencies affect bandwidth test results. Use the command hrut_somstatus to check DDR status information.

root@buildroot:/# cat /sys/class/socinfo/ddr_type
lpddr4

root@buildroot:/# hrut_somstatus
=====================1=====================
temperature-->
        DDR      : 54.1 (C)
        BPU      : 53.4 (C)
        CPU      : 53.5 (C)
cpu frequency-->
              min(M)    cur(M)  max(M)
        cpu0: 300       1500    1500
        cpu1: 300       1500    1500
        cpu2: 300       1500    1500
        cpu3: 300       1500    1500
        cpu4: 300       1500    1500
        cpu5: 300       1500    1500
        cpu6: 300       1500    1500
        cpu7: 300       1500    1500
bpu status information---->
              min(M)    cur(M)  max(M)  ratio
        bpu0: 500       1000    1000    0
ddr frequency information---->
              min(M)    cur(M)  max(M)
        ddr:  266       4266    4266
GPU gc8000 frequency information---->
              min(M)    cur(M)  max(M)
        gc8000:  200    1000    1000

Manually Set DDR Frequency: For example, set DDR frequency to 4266 MHz using the following commands:

root@buildroot:/# echo userspace >/sys/class/devfreq/soc\:ddrc-freq/governor
root@buildroot:/# echo 4266000000 >/sys/class/devfreq/soc\:ddrc-freq/userspace/set_freq

2. Ensure the stream test binary exists under /app/platform_samples/chip_base_test/09_ddr_bandwidth/. If not, recompile it in that directory:

root@buildroot:/# cd /app/platform_samples/chip_base_test/09_ddr_bandwidth

root@buildroot:/# cp /opt/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu/aarch64-none-linux-gnu/lib64/libgomp.a .

root@buildroot:/# /opt/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-gcc -O3 -fopenmp -DNTIMES=100 stream.c -L./ -lgomp -o stream

4.5.11.3. Test Method

After completing the preparation steps, run the test command:

cd /app/platform_samples/chip_base_test/09_ddr_bandwidth
./stream

Wait approximately 10 seconds to obtain the following output:

-------------------------------------------------------------
STREAM version $Revision: 5.10 $
-------------------------------------------------------------
This system uses 8 bytes per array element.
-------------------------------------------------------------
Array size = 10000000 (elements), Offset = 0 (elements)
Memory per array = 76.3 MiB (= 0.1 GiB).
Total memory required = 228.9 MiB (= 0.2 GiB).
Each kernel will be executed 100 times.
 The *best* time for each kernel (excluding the first iteration)
 will be used to compute the reported bandwidth.
-------------------------------------------------------------
Number of Threads requested = 8
Number of Threads counted = 8
-------------------------------------------------------------
Your clock granularity/precision appears to be 1 microseconds.
Each test below will take on the order of 19433 microseconds.
   (= 19433 clock ticks)
Increase the size of the arrays if this shows that
you are not getting at least 20 clock ticks per test.
-------------------------------------------------------------
WARNING -- The above is only a rough guideline.
For best results, please be sure you know the
precision of your system timer.
-------------------------------------------------------------
Function    Best Rate MB/s  Avg time     Min time     Max time
Copy:            9504.6     0.017268     0.016834     0.017501
Scale:          12742.9     0.012639     0.012556     0.012778
Add:            11429.7     0.021100     0.020998     0.021241
Triad:          11437.3     0.021061     0.020984     0.021313
-------------------------------------------------------------
Solution Validates: avg error less than 1.000000e-13 on all three arrays
-------------------------------------------------------------

Explanation of Key Results:

The four items in the test results — Copy, Scale, Add, and Triad — represent the bandwidth measurements. The test principles for these four operations are illustrated in the figure below:

image-20240310220251394

  • Copy: Reads a value from one memory location and writes it to another.

    • Test Description: In the Copy test, the system copies content from one array to another. This is the most basic memory bandwidth test, primarily evaluating performance during simple memory-to-memory data transfers.

    • Bandwidth Result: 9504.6 MB/s

  • Scale: Reads a value from memory, performs a multiplication, and writes the result to another memory location.

    • Test Description: The Scale test involves not only memory bandwidth but also CPU computation, thus better reflecting the collaborative performance between processor and memory.

    • Bandwidth Result: 12742.9 MB/s

  • Add: Reads two values from memory, performs an addition, and writes the result to another memory location.

    • Test Description: The Add test simulates adding two arrays and storing the result in a third array, testing bandwidth demands under parallel CPU and memory operations.

    • Bandwidth Result: 11429.7 MB/s

  • Triad: Combines Copy, Scale, and Add operations. Specifically, it reads two values a and b from memory, computes a + scalar * b, and writes the result to another memory location.

    • Test Description: Triad involves both array addition and scaling, making it a composite operation that includes computation, addition, and memory access.

    • Bandwidth Result: 11437.3 MB/s

  • Meaning of Output Values:

    • Best Rate MB/s (Peak Rate): The highest memory transfer rate achieved during the operation, in megabytes per second (MB/s), indicating peak performance.

    • Avg time (Average Time): The average execution time per operation in seconds, representing average latency.

    • Min time (Minimum Time): The shortest execution time among all iterations, in seconds, indicating the best single performance.

    • Max time (Maximum Time): The longest execution time among all iterations, in seconds, indicating the worst-case performance.

4.5.11.4. Test Metrics

DDR bandwidth is typically calculated based on memory clock frequency and bus width using the following formula:

Bandwidth (MB/s) = Memory Clock Frequency (MHz) * 2 * Bus Width (bit) / 8

On the x5 platform, the DDR memory frequency is 4266 MHz (2133 × 2), and the bus width is 32 bits (i.e., 4 bytes). Therefore, the theoretical bandwidth is:

Bandwidth (MB/s) = 4266 MHz * 4 Byte = 17064 MB/s

Scoring Criteria

Actual DDR bandwidth test results are usually lower than the theoretical maximum. A practical benchmark is 60%–70% of the theoretical bandwidth. For the x5 platform, with a theoretical bandwidth of 17064 MB/s, the acceptable standard is:

Passing Criterion = 17064 * 0.6 = 10238.4 MB/s

Test Result

Taking the Triad operation — which closely resembles real-world DDR usage — as an example, its result exceeds the standard bandwidth of 10238.4 MB/s. Therefore, the test result meets the DDR bandwidth criteria and achieves the expected performance requirements.