7.4.1. About Sunrise 3 (X3) Processor

Sunrise 3 (X3) is a low-power high-performance processor. X3 can be divided into X3M and X3E according to different user application scenarios.

X3 Features please refer to below block diagram:

../../../../_images/processor_block.png

  1. CPU Specifications: X3 processor uses ARM® Cortex®-A53 as host controller processor, size of L1 Cache is 32KB, size of L2 Cache is 512KB. X3 processor can support FPU & NEON accelerations, its Typical operating frequency is 1.2GHz and can support frequency control at software level. X3M has quad-core CPUs; while X3E has build-in dual-core CPUs.

  2. BPU Specifications: Brain Processing Unit (BPU) is an accelerating IP core based on D-Robotics’ own-developed Bernoulli2 microarchitecture. Wherein, typical operating frequency of X3M’s dual-core BPUs is 1.2GHz, while typical operating frequency of X3E’s dual-core BPUs is 0.6GHz. Peak computes of the 2 can reach 5 TOPs and 3 TOPs respectively.

Note

X3’s built-in 2 BPU Cores provide very flexible multi-core scheduling capabilities for business-level model scheduling, including:

  1. Single frame single core : single model inference is manually scheduled to a single BPU Core for inference. Thus, for scenarios such as detection+classification, the high priority models of full graph detection can be physically isolated from some low priority models.

  2. Single-frame dual-core : single model inference uses hardware resources of two BPU Cores for inference simultaneously, achieving true dual-core execution capability, which can significantly reduce the latency of single model inference.

In the case that resources such as DDR do not reach the bottleneck, single-frame single-core can guarantee the scheduling inference isolation of two BPU cores. The multi-threaded single-frame dual-core scenario can achieve a double improvement in inference FPS. In single-frame dual-core scenario, it can significantly reduce the single model inference latency for large models. However, in multi-threaded multi-frame dual-core scenarios, it will not achieve a double improvement in FPS because of the dual-core scheduling overhead.

  1. Video Channel Capability: X3 processor provides complete video channels such as Video In, Video Out, Video CODEC (video codec) and Image Process (image codec), please refer to the below picture for details:

../../../../_images/processor_video.png

  • Video In module supports MIPI and DVP image sensor inputs. Wherein, MIPI Rx is divided into Rx0, Rx1/3 and Rx2, there are 8 lanes in total, design bandwidth of each lane can support sensor inputs e.g. 2Gbps, YUV422 8/10bit and Raw 8, 10, 12, 14.

  • SIF module: carries the forwarding work from the virtual channel of Video In input to the downstream ISP/IPU module, and supports forwarding Video In data to the third-party processor directly through the function of bypass bypass.

  • ISP module: supports LSC/LDC/DIS/DPC/SNR, etc., which can get high quality images in wide dynamic and low illumination scenes. It also provides ISP Tuning tool to support users to do ISP debugging by themselves.

  • VPS hardware: provides image processing capabilities such as scaling, mirroring, rotation, correction, flow control, and pyramid. The hardware consists of a single IPU, a single Pyramid PYM, and two GDCs. The software uses grouping to implement time-division multiplexing hardware, supporting up to 8 groups of time-division multiplexing.

  • VENC/VDEC module: offers at maximum 8M@60fps H.265 and 8M@30fps H.264 encoding/decoding capacities. as well as 16M pixels JPEG encoding/decoding capacity.

  • Video Out module: supports BT1120, BT656 and MIPI etc output scenarios.

Note

Video In module can support not only MIPI and DVP RAW type sensor inputs, it also can support USB sensor input. Typically, it obtains USB input images in JPEG etc. formats from USB driver, then decode images using the VDEC module and dumps YUV data to VPS module.

More information about basic video channel and USB camera usages please refer to basic APIs of system software, or simplify your usage using the VideoSource application development component.

More information about X3’s other peripherals and ports please refer to X3M/X3E Datasheets.